The invention relates to a digital to analogue converter. The invention further relates to an analogue to digital converter. The invention has particular, though not exclusive, application in sigma delta converters.
In a sigma delta analogue to digital (A/D) converter there is a requirement for a digital to analogue (D/A) converter to complete the feedback loop. It is known that the linearity performance of this D/A converter determines the overall linearity of the whole system. In many systems the quantisation is made of 1- bit precision which avoids any possibility of linearity problems, since the transfer function should be ideal.
In a sigma delta A/D converter with multibit quantisation the issue of linearity assumes major importance. Clearly the elements which determine the magnitude of the signal quanta must be defined with great precision as these will set the static linearity of the D/A converter. Such factors as optimum choice of transistor or resistor size, common centroid layout can be used to optimise this static linearity.
In a switched current sigma delta A/D converter the feedback D/A converter presents its signal output to the input of the first integrator (or possibly differentiator) in the noise shaping filter. Signal summation, i.e. of the input and feedback currents, is achieved by simple connection of wires. In such switched current circuits there is always a settling error due to the time constant formed primarily by the total load capacitance at the summing node and the g.sub.m of the storage MOS transistor. Account is normally taken of this in the design and organisation of the storage cells. Any settling error should ideally be very small in absolute terms as there may be a non-linear relationship between the proportion of the error and the incoming signal. Such a variation of settling error will manifest itself as distortion in the signal.
The most convenient form for a current mode D/A converter is to use current sources (or sinks) comprising appropriately biassed MOS transistors which are selectively switched to a current summing node under the control of the applied digital code. Each of these current sources has its own parasitic capacitance to ground, principally due to the drain-bulk capacitances of the MOS transistors. As a result the total capacitance at the summing node (which also forms the input node of the A/D converter) is a function of the applied digital code. Consequently there is a corresponding variation in the settling time of the first integrator and hence a code dependent settling error in the signal stored. This presents a serious risk of distortion, especially in a design optimised for high sample rates where settling time is traded with acceptable sampling error with some precision.
In an ideal situation the capacitance at the input node should be kept to an absolute minimum but doing so implies the use of very small transistors which bring other trade offs into question, and so this strategy is quite constrained.